Field of the Invention
The present invention relates to a semiconductor component having an MIM capacitor and to an associated fabrication method.
To produce integrated electronic circuits, integrated passive components such as resistors, inductors and capacitors are also needed. For many applications, integrated capacitors need to have series resistances and losses whose magnitudes are as negligible as possible, while having a low area requirement and a low coupling to the substrate. The demand for low series resistances can be met ideally by using metal-insulator-metal (MIM) capacitors. If the metallization planes and intermetal dielectrics normally present in a multilayer metallization are used, capacitors with a very small specific capacitance per unit area (typically below 0.1 fF/μm2) and relatively high tolerances above 20% can be produced. For optimized MIM capacitors, a separate insulating layer and usually a separate thin top metal electrode are generally used.
When integrating an MIM capacitor into a fabrication process for an integrated circuit, there are fundamentally two problems. The process cycle and to some extent also the layer sequence are significantly changed to some extent in the case of the usual methods. The differences between the fabrication methods for components with an integrated MIM capacitor and without an MIM capacitor result in different properties for the metallization system, particularly as regards reliability of the circuit. It is also difficult to achieve high specific capacitance per unit area values for the MIM capacitor, since reliability and tolerance problems quickly arise when using relatively thin capacitor dielectrics. The reason for this is that the typical granular structure of the bottom electrode, which is normally AlCu or AlSiCu, results in that the electrode has a relatively rough surface which can even change in the rest of the process cycle. In addition, with the normal method, the surface is subjected to a series of process steps that can impair the surface quality further. Following deposition and before the top electrode is applied, the capacitor dielectrics are also subjected to process steps which can adversely affect their surface or their layer property.
U.S. Pat. No. 5,391,905 describes an integrated circuit and an associated method for fabricating the circuit, where a top electrode made of polysilicon for a capacitor is deposited together with a contact electrode for a transistor after a bottom electrode made of polysilicon for the capacitor and a capacitor dielectric have been produced.
Published, Non-Prosecuted German Patent Application DE 198 38 435 A1 describes a method for fabricating a semiconductor memory where a bottom capacitor electrode made of polysilicon is deposited into an opening in an insulating film.